Abstract—As the Optical Network-on-Chip (ONoC) becomes a candidate solution for the communication infrastructure of the Systems-on-Chip (SoC), the development of proper hierarchical models and tools for its design and analysis, specific to its heterogeneous nature, becomes a necessity. This work presents a novel protocol stack architecture for the ONoC. The proposed protocol stack is a 4-layered hardware stack consisting of the physical layer, the physical-adapter layer, the data link layer, and the network layer. It allows the modular design of each ONoC building block that boosts the interoperability and design reuse of the ONoC. Using this protocol stack architecture, this paper also introduces the micro-architecture of a new router called Electrical Distributed Router (EDR) as a wrapper for the ONoC. The proposed protocol stack has been modeled and integrated inside an industrial simulation environment (ST OCCS GenKit) using an industrial standard (VSTNoC) protocol.