This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50Ω differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of −25dBm for a BER= 10−12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dBΩ, 1.5GHz bandwidth and occupies a chip area of 0.16mm2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.