A reliable factorial experimental design was applied to DRIE for specifically producing high-aspect ratio trenches. These trenches are to be used in power electronics applications such as active devices: deep trench superjunction MOSFET (DT-SJMOSFET) and passive devices: 3D integrated capacitors. Analytical expressions of the silicon etch rate, the verticality of the profiles, the selectivity of the mask and the critical loss dimension were extracted versus the process parameters. The influence of oxygen in the passivation plasma step was observed and explained. Finally, the analytical expressions were applied to the devices objectives. A perfectly vertical trench 100-μm deep was obtained for DT-SJMOSFET. Optimum conditions for reaching high-aspect ratio structures were determined in the case of high-density 3D capacitors.